1. Field of the Invention
The present invention relates to method for manufacturing semiconductor device, and in particular to an improved method for manufacturing semiconductor device wherein the gate oxide films in the cell region, VPP peripheral circuit region and VDD peripheral circuit region are formed to have different thicknesses from one another so that the threshold voltage of the cell transistor may be increased to a desired value as well as increasing the operation speed of the transistor and suppress the short channel effect.
2. Description of the Background Art
An integrated circuit includes a cell region where cell transistors for storing data are formed, a VPP peripheral circuit region where transistors used for generating a VPP voltage and as paths for transferring the VPP voltage are formed, and a VDD peripheral circuit region where transistors to which a VDD or a VCORE voltage which is lower than the VPP voltage are formed. A conventional transistor formed in above regions and method for manufacturing the same will now be described.
FIGS. 1A and 1B are cross-sectional views illustrating a conventional transistor of semiconductor device in a cell region, wherein FIGS. 1A and 1B respectively illustrate cross-sections perpendicular and parallel to a word line in a cell region.
Referring to FIGS. 1A and 1B, a recessed device isolation film 65 defining an active region is disposed on a semiconductor substrate 10. A sidewall oxide film 40 and a liner nitride film 50 are disposed at an interface of the semiconductor substrate 10 and the recessed device isolation film 65. A stacked structure 80+90 of a first gate oxide film pattern 80 and a second gate oxide film pattern 90 is disposed at an interface of a gate structure 130 which is a word line comprising a stacked structure of the lower gate electrode 100, the upper gate electrode 110 and the hard mask pattern 120 and the semiconductor substrate 10.
FIGS. 2A and 2B are cross-sectional views illustrating a conventional transistor of semiconductor device in VPP peripheral circuit region, wherein FIGS. 2A and 2B respectively illustrates cross-sections perpendicular and parallel to gate structures of a transistor in a VPP peripheral circuit region.
Referring to FIGS. 2A and 2B, a device isolation film 60 defining an active region is disposed on a semiconductor substrate 10. A sidewall oxide film 40 and a liner nitride film 50 are disposed at an interface of the semiconductor substrate 10 and the device isolation film 60. A stacked structure 80+90 of a first gate oxide film pattern 80 and a second gate oxide film pattern 90 is disposed at an interface of a gate structure comprising a stacked structure of the lower gate electrode 100, the upper gate electrode 110 and the hard mask pattern 120 and the semiconductor substrate 10.
FIGS. 3A and 3B are cross-sectional views illustrating a conventional transistor of semiconductor device in VDD peripheral circuit region, wherein FIGS. 3A and 3B respectively illustrates cross-sections perpendicular and parallel to gate structures of a transistor in a VDD peripheral circuit region.
Referring to FIGS. 3A and 3B, the structure of the transistor in the VDD peripheral circuit region is similar to that of the transistor in the VPP peripheral circuit region shown in FIGS. 2A and 2B. However, only a second gate oxide film pattern 90 is disposed at an interface of a gate structure 130 comprising a stacked structure of the lower gate electrode 100, the upper gate electrode 110 and the hard mask pattern 120 and the semiconductor substrate 10. That is, the thickness of the gate oxide film differs from those of the gate oxide film in the cell region and the VPP peripheral circuit region. The thickness of the gate oxide film of the transistor in the cell region shown in FIGS. 1A and 1B is substantially the same as that of the transistor in the VPP peripheral circuit region shown in FIGS. 2A and 2B, and larger than that of the transistor in the VDD peripheral circuit region shown in FIGS. 3A and 3B.
FIGS. 4A through 4F are cross-sectional views illustrating a conventional method for manufacturing transistor of semiconductor device, wherein (i) and (ii) of FIG. 4 respectively illustrate cross-sections perpendicular to and parallel to a word line in a cell region, and (iii) and (iv) of FIG. 4 respectively illustrate cross-sections perpendicular to gate structures of a transistor in a VPP peripheral circuit region and in a VDD peripheral circuit region.
Referring to FIG. 4A, a pad oxide film 20 and a pad nitride film 30 are sequentially formed on a semiconductor substrate 10 including a cell region where cell transistors are formed, a VPP peripheral circuit region where transistors used for generation and transfer of VPP voltage are formed, and a VDD peripheral circuit region where VDD transistors are formed. Thereafter, a predetermined region of the pad nitride film 30, the pad oxide film 20 and the semiconductor substrate 10 are etched to form a device isolation trench (not shown). The semiconductor substrate 10 at a top corner of the device isolation trench is etched so that the top corner is rounded. A sidewall oxide film 40 and a liner nitride film 50 are then formed on the entire surface of the semiconductor substrate 10 including the device isolation trench. Thereafter, an oxide film (not shown) for the device isolation film 60 is formed on the entire surface of the semiconductor substrate 10 and then planarized until the pad nitride film 30 is exposed to form the device isolation film 60 defining an active region 10a. 
Now referring to FIG. 4B, a predetermined thickness of the device isolation film 60 is etched so that the height of the device isolation film 60 is reduced. Thereafter, the pad nitride film 30 is removed by etching. A predetermined amount of the sidewall oxide film 40 and the liner nitride film 50 is also etched during the etching process of the pad nitride film 30. Thereafter, the pad oxide film 20 is removed by etching to expose the semiconductor substrate 10. A buffer oxide layer 70 is then formed on the exposed semiconductor substrate 10. Next, an impurity is selectively implanted into the semiconductor substrate 10 to form a deep n-well (not shown), cell p-well (not shown), p-well (not shown) and an n-well (not shown). A channel implant process for adjusting threshold voltage and punch-through voltage is then performed.
Referring to FIG. 4C, a photoresist film pattern (not shown) exposing the cell region is formed. A predetermined thickness of the device isolation film 60 in the cell region is etched using the photoresist film pattern as an etching mask. Thereafter, the semiconductor substrate 10 is subjected to an angled implant process for adjusting an impurity concentration of the channel region using the photoresist film pattern as an implant mask to inject an impurity containing boron into the semiconductor substrate 10 in the cell region. The photoresist film pattern is then removed.
Referring to FIG. 4D, the exposed portion of liner nitride film 50 is removed. Thereafter, the buffer oxide layer 70 and the sidewall oxide film 40 are removed by etching to expose a portion of the semiconductor substrate 10. The exposed portion of the semiconductor substrate 10 is then oxidized to form a first gate oxide film 80. Next a photoresist film pattern (not shown) exposing the VDD peripheral circuit region is then formed. An impurity for controlling threshold voltage is implanted into the semiconductor substrate 10 in the VDD peripheral circuit region using the photoresist film pattern as an implant mask. Thereafter, an exposed portion of the first gate oxide film 80 in the VDD peripheral circuit region is removed by etching using the photoresist film pattern as an etching mask. The photoresist film pattern is then removed.
Referring to FIG. 4E, the first gate oxide film pattern 80 is subjected to a cleaning process. Thereafter, a second gate oxide film 90 is formed on surfaces of the first gate oxide film 80 and the semiconductor substrate 10 in the VDD peripheral circuit region. Therefore, the thickness of the gate oxide film in the cell region and the VPP peripheral circuit region are substantially the same as that of a stacked structure 80+90 of the first gate oxide film 80 and the second gate oxide film 90.
Referring to FIG. 4F, a conductive layer (not shown) for lower gate electrode is formed on an entire surface of the semiconductor substrate 10 and then planarized. A conductive layer (not shown) for upper gate electrode and a hard mask layer (not shown) are sequentially stacked on the conductive layer for lower gate electrode. The hard mask layer, the conductive layer for upper gate electrode and the conductive layer for lower gate electrode are etched via a photolithography and etching process using a gate mask (not shown) to form a gate structure 130 comprising a stacked structure of the lower gate electrode 100, the upper gate electrode 110 and the hard mask pattern 120. Thereafter, a source/drain region (not shown) is formed on the semiconductor substrate 10 at both sides of the gate structure 130.
As described above, in accordance with the conventional semiconductor device and method for manufacturing the same, VPP voltage is applied to the transistor in the cell region through VPP voltage generating circuit and path in the VPP peripheral circuit region and VDD or VCORE voltage which is lower than VPP voltage is applied to other parts of the semiconductor device. Therefore, the thickness of the gate oxide film in the cell region and the VPP peripheral circuit region is the same which is thicker than that of the gate oxide film in the VDD peripheral circuit region. However, in case of a cell transistor having a fin gate structure, because two or three sides of the active region are surrounded by the gate electrode, threshold voltage is decreased due to more than the liner nitride film 50% decrease in QD,MAX which is a depletion charge induced by the voltage applied to the gate electrode when the silicon substrate is completely depleted by the gate voltage.
In order to increase the threshold voltage, methods such as increasing channel doping concentration NA to increase QD,MAX, using a gate electrode having a different work function to increase ΦMS or adding a electron trap in the gate oxide film to increase −QOX have been proposed.
However, the method of increasing channel doping concentration increases junction leakage current and deteriorates refresh characteristics of the device due to increase in electric field in pn junction region, the method of using a gate electrode having a different work function increases the number of processes and degrades the reliability of the device and the method of adding a electron trap in the gate oxide film results in degradation of the reliability of the device.
In accordance with conventional art, the threshold voltage of a fin gate transistor cannot be the same as that of the planar transistor when the thickness of the gate oxide film of the cell transistor is the same as that of the transistor in the VPP peripheral circuit region.